Main optoelectronic specifications

*1 Focal Plane Chip Temperature = -20℃

*2 Under the condition near the optical signal half-well, the percentage of pixels where the deviation between the response signal and the average value is less than 50%

*3 Chip Temperature = -20℃, MG Gain, Integration Time 2ms, IWR Mode

The above data were obtained without enabling the CDS mode during testing

Mechanical Parameter

Operating Environment & Power Consumption Spec

TEC Disabled, Ambient Temperature = 25℃, Number of Readout Channels = 8, Power Consumption Control Gear = 100%

Mechanical Specification 

This InGaAs area array detector adopts a metal package with vacuum sealing. The metal shell is made of FeNiCoSi alloy, with a Ni/Au electroplated layer on the surface. The window is bonded via In-based brazing, and the cover is sealed by resistance welding. The external dimensions of the detector are 60mm (Length) x 44mm (Width) x 11.55mm (Height).

Thirty-six pins (0.7mm x 0.25mm) are led out from the side of the shell, arranged in a single-row "linear" pattern on both sides. The spacing between adjacent pins on one side is 1.27mm. These pins are used for the input of focal plane power supply and commands, the input of thermoelectric cooler (TEC) power supply, and the electrical lead-out of focal plane detection signals and temperature sensor signals. Additionally, two pins (1.0mm x 0.5mm) on the side are used for getter activation. Four through-holes (Φ2.5mm) are distributed on both sides of the package for detector fixation.

Optical Specification

optical structure

This detector adopts a 640×512-pixel InGaAs focal plane array, with a pixel pitch of 15 μm. The pixels are square-shaped, and each photosensitive pixel has a size of 15 μm × 15 μm.

This detector features a designed distance of 3.4 mm between its photosensitive surface and the upper surface of the package structure, 2.45 mm between its photosensitive surface and the lower surface of the optical window, and 1.05 mm between its photosensitive surface and the lower surface of the diaphragm.

The optical window is made of sapphire, with a thickness of 0.9 mm and a refractive index of 1.76. Its surface is coated with an anti-reflective (AR) coating, ensuring a transmittance of >95% within the response wavelength range. The light-transmitting area of the optical window measures 15 mm × 11 mm, while the light-transmitting size of the diaphragm is 10.2 mm × 8.2 mm.

The center of the photosensitive surface is aligned with the center of the detector, with a relative positional deviation of ≤0.05 mm and a relative rotational displacement of ≤0.02 mm.

Relative Spectral Response (Typical Value)

Electrical Specification

Pin Defination

*It is recommended that the supply voltage be adjusted according to the focal plane temperature: 2.88V@RT, 2.86V@0℃, 2.84V@-20℃

Precautions:

The DC input directly affects the overall noise of the detector. Therefore, there are the following requirements for the ripple noise of the DC input power supply:

Ripple noise requirements for each power supply voltage:

a) VDDA1: < 1mV;

b) VDDA2: < 10mV;

c) VD33: < 10mV;

d) VD18: < 10mV;

Load requirements for signal output terminals (VOUT1 - VOUT8): Cload < 25pF; Rload > 100kΩ;

Range of logic output signals (ROW_ST, ST): The logic output signals are high - and low - level digital signals, where

a) Low level: 0 - 0.3V;

b) High level: (VD18 - 0.3V) - VD18;

c) Load requirements for logic output terminals: Cload < 15pF

Diagram of Detector Working Principle and Connection Method

Detector Timing Description

 ITR Mode

The schematic diagram of the readout circuit driving timing pulses is as follows.

Timing Details:

a) The serial port command word input must be completed before the start of integration;

b) INT, as the integration time control signal, has both high and low level durations equal to an integer number of Tclk;

c) After the completion of the current frame integration Tint, a period of Thold (93 T_clk) is required before starting the readout of the integration signal. During the readout process of the current frame signal, the readout starts row by row from the first row. After each row is read out, a period of Td (32 T_clk) is required before starting the readout of the integration signal of the next row, until all signal readouts are completed;

d) When the readout of the current frame integration signal starts, the detector synchronously outputs ST and ROW_ST voltage signals, where ST is the frame output flag; ROW_ST is the row output flag, and a high level indicates that the signal is being read out. The high level width is Tclk × C/N, where C is the number of columns and N is the number of output channels. The interval between adjacent high levels is Td until the readout of the integration signal is completed;

e) In each output channel, reading out the integration signal of one pixel requires one main clock T_clk. The readout time Tout = C × R/N × T_clk + (R-1) × Td, where R is the number of rows; the working frame period T_frame = T_int + T_hold + T_out.

IWR Mode

The schematic diagram of the readout circuit driving timing pulses is as follows.

Timing Details:
a) The serial port command word input must be completed before the start of integration;
b) In this mode, the integration of the pixel signal of the current frame and the readout of the integration signal of the previous frame are completed simultaneously within one frame period;
c) INT, as the integration time control signal, has both high and low level durations equal to an integer number of T_clk, and the low level width of INT must be greater than 45 T_clk;
d) After the completion of the current frame integration Tint, a period of Thold (93 T_clk) is required before starting the readout of the integration signal. During the signal readout process, the readout starts row by row from the first row. After each row is read out, a period of Td (32 T_clk) is required before starting the readout of the integration signal of the next row, until all signal readouts are completed;
e) When the readout of the current frame integration signal starts, the detector synchronously outputs ST and ROW_ST voltage signals, where ST is the frame output flag; ROW_ST is the row output flag, and a high level indicates that the signal is being read out. The high level width is T_clk × C/N, and the interval between adjacent high levels is Td until the readout of the integration signal is completed;
f) In each output channel, reading out the integration signal of one pixel requires one main clock Tclk. The readout time T_out = C × R/N × T_clk + (R-1) × T_d;
g) The frame period is approximately equal to the readout time, and the overall frame period: T_frame ≥ T_hold + T_out + 320T_clk.

NDRO Mode

The schematic diagram of the readout circuit driving timing pulses is as follows:

Timing Details:

a) In the serial port command word configuration, after setting the coding bit that controls NDRO readout to enable the NDRO mode, the detector continues to perform integration according to the IWR readout mode, but does not conduct signal sampling;

b) The output signal value remains the integration signal of the last frame before entering the NDRO mode, and the held signal of this frame is output in a repeated cycle;

c) After setting the coding bit that controls NDRO readout to disable the NDRO mode, the detector enters the IWR readout mode. However, the held signal is still output in this frame, and the normal IWR integration signal is output in the next frame.

IMRO Mode 

The schematic diagram of the readout circuit driving timing pulses is as follows:

Timing Details:

a) In the serial port command word configuration, after setting the coding bit that controls IMRO readout to enable the IMRO mode, the detector continues to perform signal sampling according to the IWR mode, but the integration proceeds continuously, and the output signal value is the result of integration within the previous Tframe;

b) After modifying the command word to disable the IMRO mode, the detector enters the IWR readout mode.

Notes: The input clock CLK and the rising/falling edges of INT must satisfy a certain relationship. Both the rising edge and falling edge of INT should lag behind the falling edge of CLK (typically by 10ns), but the delay time must not exceed 0.25 times the time width of the main clock CLK.

Serial Port Command Word Configuration

Definition of Each Bit of the Command Word

Gain [1:0] - Gain Level Control

Control Mode

Notes

a) The IMRO mode is controlled by the IMRO (Multiple Integration Readout) command word; the NDRO mode is controlled by the NDRO (Non-Destructive Readout) command word; the CDS mode is controlled by the CDS_MODE command word;

b) The priority order of each command word is IMRO > NDRO > CDS_MODE, and Gain[1] > CDS_MODE;

c) During the process of switching from "CDS mode" to "Non-CDS mode", it is recommended to first switch to "Non-CDS Low Gain Mode", and then switch to "Normal Non-CDS Operating Mode".

Image Flip Control: UPCOL, UPROW

When the TEC pins are oriented to the left, the default origin (1, 1) is at the bottom-left corner, and the readout proceeds toward the top-right corner (640, 512);

*Note: The above diagram is a schematic of the readout sequence when the TEC pins are oriented to the left and 8-channel readout is enabled.

Preset Window Size Control: SizeA, SizeB

Custom Window Setting

a) The number of window rows is independent of the number of output channels.

Starting row: 0 ≤ Rstart ≤ 508

Ending row: 0 ≤ Rfinal ≤ 511

b) 2-channel output (NBOUT[1:0] = 2’b00 or 2’b01):

Starting column: 2 × Cstart, where 0 ≤ Cstart ≤ 318

Ending column: 2 × Cfinal + 1, where Cstart + 1 ≤ Cfinal ≤ 319

Minimum window size: 4 (rows, R) × 4 (columns, C)

c) 4-channel output (NBOUT[1:0] = 2’b10):

Starting column: 4 × Cstart, where 0 ≤ Cstart ≤ 158

Ending column: 4 × Cfinal + 3, where Cstart + 1 ≤ Cfinal ≤ 159

Minimum window size: 4 (rows, R) × 8 (columns, C)

d) 8-channel output (NBOUT[1:0] = 2’b11):

Starting column: 8 × Cstart, where 0 ≤ Cstart ≤ 78

Ending column: 8 × Cfinal + 7, where Cstart + 1 ≤ Cfinal ≤ 79

Minimum window size: 4 (rows, R) × 16 (columns, C)

Power Consumption Control: Pctrl [1:0]

Number of Output Channels: NBOUT[1:0]

Pixel Power Consumption Control: Ppix [2:0]

Column BUF Power Consumption Control: Pbuf[1:0]

Driver Signal Setup Time Control: Pfol [1:0]

Output BUF Power Consumption Control: Pout

Integration Preparation Time Control: Tpre [2:0]

The INT high-level width (i.e., integration time) must be longer than the integration preparation time. To achieve the shortest integration time, the configuration of Tpre [2:0] should be set to 3b’111.

In CDS mode (Correlated Double Sampling mode), the integration time must be longer than the sum of the Tpre [2:0] time and the Tcds time.

Anti-blooming Function Control BLM_EN and BLM_CTL [2:0]

T_cds Clock Count Control Signal: T_cds

In CDS mode (Correlated Double Sampling mode), the integration time must be longer than the time configuration of T_CDS.

Bandwidth Limitation Control: OUTbw

Configuration Method for Short Integration Applications

When CDS_MODE = 1’b0 (non-CDS mode) and Tpre = 3’b111 are set simultaneously, the circuit enters non-CDS mode. In this mode, the circuit supports configurations where the minimum integration time is longer than 3Tclk.

This configuration is suitable for application scenarios requiring short exposure times, such as active illumination gated imaging.

Recommended Peripheral Circuit Diagram for Detector

Thermal Parameters

Thermoelectric Cooler (TEC) Characteristics

A 3-stage thermoelectric cooler (TEC) is integrated into the detector. The center of the heat dissipation surface aligns with the center of the detector's lower surface, and the heat dissipation area must be ≥ 36mm × 30mm. Its performance parameters are shown in the table below:

*This performance indicator specifically refers to the temperature difference between the focal plane and the heat dissipation surface of the package structure.

Characteristics of the Temperature Sensor

This product uses a thermistor as the temperature sensor. Within the operating temperature range, the corresponding relationship between the thermistor's resistance value and temperature is shown in the figure below:

Typical Corresponding Relationship Between Thermistor Resistance and Temperature

Corresponding Relationship Between Thermistor Resistance and Temperature (Expressed by the Following Formula):

T1: Test target temperature, Unit: ℃

T2: Reference point temperature, Unit: ℃. Within the range of -70~30℃, the typical values of reference temperature are -40℃ or -10℃, and a reference temperature value close to the target temperature should be selected.

R1, R2: Thermistor resistance values corresponding to T1 and T2 respectively, Unit: kΩ

B: Thermistor coefficient. Within the range of -70~30℃, the typical value of B-40/-10 is 2854.43 (with a deviation of ±2%), and the temperature deviation calculated from this typical value is ±0.5℃.

Notes

a) During the installation of the TEC, attention should be paid to the additional resistance introduced by the external electrical structure. If the additional resistance exceeds 10% of the TEC resistance, the I-V curve must be recalibrated.

b) It is recommended to connect the TEC in a way that minimizes the connection resistance. If pin soldering is necessary, short-circuit grounding protection should be implemented. The local temperature during pin soldering must be ≤ 250℃, and the soldering duration must be < 10s.

c) If higher measurement accuracy is required within a small temperature range, the B-value can be calculated independently as needed.

d) Before turning on the TEC, it is mandatory to confirm the following: the temperature sensor is working normally, the heat dissipation surface is in full contact with the heat sink, the heat dissipation surface meets the required size, and the heat sink is functioning properly. It is not recommended to turn on the TEC without installing the heat sink or when the heat sink is not working.

e) When turning on the TEC for the first time, the current or voltage should be gradually applied starting from 0A or 0V. Meanwhile, monitor the temperature change until the preset temperature is reached.

f) Since the detector performance is affected by temperature, the TEC should be turned on first and stabilized at the target temperature before activating the detector. It is not recommended to operate the detector in an environment with fluctuating temperatures.

g) When the detector is not in use for an extended period, power supply to the TEC should be stopped to extend the TEC’s service life.

h) The cooling effect of the detector is related to the ambient temperature, power supply performance, and heat dissipation status. It is recommended to properly match the heat dissipation system according to the actual operating environment and the required detector performance.

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