Key Parameter
Main optoelectronic specifications
Parameter | Typical Value |
Response Spectral Range (µm)*¹ | 1.30 ±0.05 ~ 2.50 ±0.05 |
Peak Quantum Efficiency (%) | ≥60 |
Dark Current Density (µA/cm²)*¹ | <5 |
Effective Pixel Rate (%)*²³ | ≥98 |
Response Non-Uniformity (%)*³ | <8 |
Readout Mode | IWR, ITR, optional |
Readout Speed (MHz) | Single channel 10 |
Max Frame Rate (fps) | 20k |
Gain Levels | 8 |
Saturation Voltage (V) | 1.6 |
Conversion Gain (nV/e⁻) | Gain Level 1: 16000 Gain Level 2: 8000 Gain Level 3: 4000 Gain Level 4: 2665 Gain Level 5: 1775 Gain Level 6: 840 Gain Level 7: 325 Gain Level 8: 160 |
*1 Focal Plane Temperature = -20℃
*2 Percentage of pixels where the pixel response signal deviation from the average value is within a certain range
*3 Test Conditions: Focal Plane Temperature = -20℃, Gain at Level 8, Integration Time = 0.5ms
Mechanical Parameter
Parameter | Typical Value |
Length × Width × Height (mm³) | 55 ×32.6 × 13 |
Weight (g) | ~78 |
Focal Plane Array Size | 512 × 1 |
Pixel Pitch (µm) | 25 |
Pixel Size (µm²) | 25 ×250 |
Active Area (mm²) | 12.8 ×0.25 |
Operating Environment & Power Consumption Spec
Parameter | Typical Value |
Operating Temperature (°C) | 0~+35 |
Storage Temperature (°C) | -5~+40 |
Typical Power Consumption (W) | <0.15 |
TEC Disabled, Ambient Temperature = 25℃, Number of Readout Channels = 8, Power Consumption Control Gear = 100%
Mechanical Specification
This detector adopts a metal packaging design, filled with high-purity nitrogen at atmospheric pressure. The metal shell is made of FeNiCoSi alloy, with a Ni/Au electroplated layer on the surface. The window is bonded via adhesive, and the cover is sealed by resistance welding. The external dimensions of the detector are 55mm (Length) × 32.6mm (Width) × 13mm (Height).
Thirty-eight pins with a diameter of Φ0.5mm are led out from the back of the shell, with a pin pitch of 1.78mm. These pins are used for the input of focal plane power supply and commands, as well as the electrical lead-out of focal plane detection signals and temperature sensor signals. Two pins with a diameter of Φ1.0mm on the side are used for connecting the thermoelectric cooler (TEC). Four through-holes with a diameter of Φ2.5mm are distributed on both sides of the package for fixing the detector.
Optical Specification
optical structure
This product uses a 512×1 element InGaAs focal plane, with 2 redundant elements on each end, that is, the total number of pixels is 516×1. In actual use, it is recommended to use the 3rd to 514th columns. The pixel shape is rectangular, the photosensitive size is 25μm×250μm, and the structure is arranged in a "one" shape, as shown in the figure below.
The optical window material is K9 glass with a thickness of 1.8mm and a transmittance of >90% in the response band. The center of the photosensitive surface is located at the center of the detector, with a relative position offset of ≤0.05mm and a relative rotation displacement of ≤0.02mm. The optical interface dimensions are shown in the figure below.
Relative Response Spectrum (Typical Value at Room Temperature)
Electrical Specification
Detector pin diagram
Pin Name | I/O | Function | Reference Value |
GND | Input | Ground | Operating current<10mA |
CLK | Input | Clock signal, provides timing reference for circuit driving | Digital voltage; High level 3.3V, Low level 0V |
VDDD | Input | Digital circuit power supply, provides voltage for digital circuits inside the detector | DC 3.3V, operating current<5mA |
VDDA | Input | Analog circuit power supply, provides voltage for analog circuits inside the detector | DC 3.3V, operating current<25mA |
SC1, SC2, SC3 | Input | Detector gain selection, controls detector output signal amplitude; see timing section | Digital voltage; High 3.3V, Low 0V |
ST | Input | Trigger pulse, marks the start of circuit signal acquisition | Digital voltage; High 3.3V, Low 0V |
RESET | Input | Reset signal, controls acquisition period duration; see timing section | Digital voltage; High 3.3V, Low 0V |
SH1, SH2, SH3 | Input | Sampling control signals, set integration time of pixels and change readout mode; see timing section | Digital voltage; High 3.3V, Low 0V |
VBOUT | Input | Buffer bias voltage, provides bias to the circuit buffer | DC 2.3V |
VBOP | Input | Amplifier bias voltage, provides bias to the signal amplifier | DC 2.3V~2.5V, recommended 2.4V |
VREF | Input | Reference voltage, provides reference value for output signal | DC 2.3V |
VNDET | Input | Detector chip common negative terminal | DC 2.3V |
VOUTR | Output | Reference signal | 0.5V~2.5V |
VOUTS | Output | Output signal, calculated from reference signal minus output signal | 0.5V~2.5V |
TS | - | Temperature sensing resistor, measures resistance to calculate operating temperature | — |
TEC+, TEC- | - | Thermoelectric cooler power supply; pin polarity as labeled | Do not exceed rated TEC voltage and current |
Precautions
*Anti-static measures shall be taken during the transportation and use of the detector.
*Before powering on the detector, check the power connection status and drive settings. Strictly ensure that the operating current of each circuit does not exceed 60mA during power supply. Short-circuiting of the signal output terminal is prohibited, and it is recommended to supply power first, then apply the timing signal for operation.
*The DC input directly affects the overall noise of the detector; therefore, the following requirements are imposed on the ripple noise of the DC input power supply:
a) VDDA ＜ 2mV
b) VDDD ＜ 10mV
c) VREF, VNDET ＜ 0.3mV
d) VBOP, VBOUT ＜ 1mV
Diagram of Detector Working Principle and Connection Method
Detector Timing Description
The overall readout circuit driving timing pulse is shown in the following figure:
IWR mode:
ITR mode:
After zooming in, the timing details at the trigger level ST are as follows:
The overall timing requirements are as follows:
Name | High level width | Initial level | Rising edge time |
CLK | 0.5 CLK cycle | Low | 0.5 CLK cycle |
RESET | Adjust according to the integration time | High |
|
SH1 |
| Low | 6μs |
SH2 | 4μs | Low | 5μs before RESET falling edge |
SH3 | 4μs | Low | 1μs |
ST | 1 CLK cycle | Low | 15μs |
1) The CLK cycle and RESET high level width can be set according to the needs. The recommended CLK frequency range is 1~10MHz, and the RESET low level width cannot be less than 2μs;
2) In IWR mode, the order of SH1, SH2, and SH3 cannot be changed. The specific integration time of the detector is the time from the falling edge of SH1 to the falling edge of SH2 in the same RESET cycle;
3) The ST high level needs to cover a complete CLK high level, and the ST rising edge needs to be within the low level of CLK. It is recommended to set the rising edge at 1/2 of the CLK low level;
4) The actual signal is read from the first CLK rising edge after the ST rising edge. The reference signal R and the output signal S are read out in sequence until the last CLK cycle before the falling edge of SH2 is reached;
5) If the width of RESET high level is not enough to read out all 516 pixels, when the next RESET high level comes, it will still start reading from the first pixel, not from the pixel that has not been read; if the width of RESET high level is too large, it will continue to be empty after reading all 516 pixels of the channel, until the RESET low level comes to reset;
6) It is recommended to use digital input voltage for SC1, SC2, and SC3, that is, always maintain 3.3V high level/0V low level;
Characteristics of the Temperature Sensor
This product uses a thermistor as the temperature sensor. Within the operating temperature range, the corresponding relationship between the thermistor's resistance value and temperature is shown in the figure below:
