512X1 Extended InGaAs Linear Detector     


The L055125M2-A InGaAs linear detector is mainly composed of a 512×1 scale InGaAs photosensitive chip, a readout circuit (ROIC) and a two-stage thermoelectric cooler (TEC), and adopts a metal package. It has the characteristics of wavelength extension and multi-level gain selection, and can be used in short-wave infrared imaging, industrial detection, color sorting and other fields.




Product model


Name Model Price
512X1 Extended InGaAs Linear Detector   [PDF]  [RFQ]

L055125M2-A
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Parameter



Key Parameter

Main Parameters of Detector

Photoelectric Properties

Index

Typical   value

Response spectrum range(μm)*1

1.30±0.05~2.50±0.05

Peak quantum efficiency(%)

≥60

Dark current density (μA/cm2)*1

<   5

Effective pixel rate (%)*2,3

≥98

Response inconsistency (%)*3

<8

Readout method

IWR, ITR, optional

Readout rate (MHz)

Single channel 10

Maximum frame rate (fps)

20k

Gain level

8

Saturation voltage (V)

1.6

Conversion gain (nV/e-)

Gain level 1: 16000

Gain level 5: 1775

Gain level 2: 8000

Gain level 6: 840

Gain level 3: 4000

Gain level 7: 325

Gain level 4: 2665

Gain level 8: 160

*1 Focal plane temperature = -20℃

*2 The deviation between the pixel response signal and the average value is less than the percentage of pixels within a certain range

*3 Test conditions: focal plane temperature = -20℃, 8th gain, integration time 0.5ms


Mechanical Property

Index

Typical value

L x W x H (mm3)

55 x 32.6 x 13

Weight (g)

~78

Focal plane scale

512 x 1

Pixel center distance (μm)

25

Pixel size (μm2)

25 x 250

Photosensitive area (mm2)

12.8 x 0.25


Operating Environment and Power Consumption Parameters

Index

Typical value

Operating environment temperature (℃)

0~+35

Storage environment temperature (℃)

-5~+40

Typical power (W)*

<0.15

*TEC is not turned on, ambient temperature = 25℃, clock frequency = 1MHz, VDDD = VDDA = 3.3V, VBOP = 2.4V, VBOUT = VREF = VNDET = 2.3V


Mechanical Parameters

This detector adopts metal packaging, filled with high-purity nitrogen at normal pressure, the metal shell is made of FeNiCoSi alloy, the surface is electroplated with Ni/Au layer, the window welding method is bonding, and the cover is resistance welding. The detector size is 55mm (L) × 32.6mm (W) × 13mm (H). There are thirty-eight Φ0.5mm pins on the shell leading out from the back, with a pin spacing of 1.78mm, which are used for the input of focal plane power supply and command, focal plane detection signal and electrical lead-out of temperature sensor; two Φ1.0mm pins on the side are used for the connection of thermoelectric cooler. There are four Φ2.5mm through holes on both sides of the tube shell for fixing the detector.

AT1.png



Optical Parameters

Optical Structure

This product uses a 512×1 element InGaAs focal plane, with 2 redundant elements on each end, that is, the total number of pixels is 516×1. In actual use, it is recommended to use the 3rd to 514th columns. The pixel shape is rectangular, the photosensitive size is 25μm×250μm, and the structure is arranged in a "one" shape, as shown in the figure below.

AT2.png

The optical window material is K9 glass with a thickness of 1.8mm and a transmittance of >90% in the response band. The center of the photosensitive surface is located at the center of the detector, with a relative position offset of ≤0.05mm and a relative rotation displacement of ≤0.02mm. The optical interface dimensions are shown in the figure below.

AT3.png

AT4.png


Relative Response Spectrum (Typical Value at Room Temperature)

AT5.png

Electrical properties

Detector pin diagram

AT6.png

Detector Pin Description

PIN

Input   / Output

Pin   Function

Reference   Value

GND

Input

Ground   wire

Current  <10mA during operation

CLK

Input

CLK   Input Clock, providing time reference for circuit drive timing

Digital   voltage;

High   level 3.3V, low level 0V

VDDD

Input

Digital   circuit power supply, providing voltage for the digital circuit in the   detector

DC   3.3V, current during operation needs<5mA

VDDA

Input

Analog   circuit power supply, providing voltage for the analog circuit in the   detector

DC   3.3V, current during operation needs<25mA


PIN

Input   / Output

Pin   Function

Reference   Value

SC1SC2SC3

Input

Detector   gain selection, controlling the output signal size of the detector, for   details on the control method, see the timing section

Digital   voltage

High   level 3.3V, low level 0V

ST

Input

Trigger   pulse, the sign that the circuit starts to collect signals

Digital   voltage

High   level 3.3V, low level 0V

RESET

Input

Reset   signal, controls the length of the circuit collection cycle,

Control   method see timing section

Digital   voltage

High   level 3.3V, low level 0V

SH1SH2SH3

Input

Sampling   control signal, sets pixel integration time,

Change   readout mode, control method see timing section

Digital   voltage

High   level 3.3V, low level 0V

VBOUT

Input

Buffer   bias, provides bias for the circuit total buffer

Voltage   DC 2.3V

VBOP

Input

Amplifier   bias, provides bias for the signal amplifier

Voltage   DC 2.3V~2.5V, recommended 2.4V

VREF

Input

Reference   voltage, provides reference value

output   signal DC 2.3V

VNDET

Input

Chip   common N

DC   2.3V

VOUTR

Output

Reference   signal

0.5V~2.5V

VOUTS

Output

Output   signal, the actual detector response signal value is obtained by subtracting   the output signal from the reference signal

0.5V~2.5V

TS

-

Temperature   measuring resistor, the resistance value is measured through two pins to   feedback the working temperature of the focal plane


TEC+TEC-

-

Thermoelectric   cooler input voltage, + pin connected to high potential, - pin connected to   high potential

Don’t   exceed the rated voltage and current of TEC

CASE

-

Grounded   together with the entire detector tube shell


ST

Input

Trigger   pulse, the sign that the circuit starts to collect signals Digital voltage

High   level 3.3V, low level 0V

RESET

Input

Reset   signal, control circuit collection cycle length, control method see timing   section

Digital   voltage

High   level 3.3V, low level 0V

NC

-

No   pin


Notes:

1) Anti-static measures should be taken during the delivery and use of the detector;


2) Before the detector is powered on, the power supply connection status and drive setting value must be checked to strictly ensure that the working current of each circuit does not exceed 60mA during the power supply process. Short circuit of the signal output terminal is prohibited, and it is recommended to supply power first and then supply timing;


3) DC input directly affects the overall noise of the detector, so the ripple noise of the DC input power supply has the following requirements:

a) VDDA<2mV

b) VDDD<10mV

c) VREF、VNDET<0.3mV

d) VBOP、VBOUT<1mV


Detector working principle and connection diagram

AT7.png

Detector Timing Description

The overall readout circuit driving timing pulse is shown in the following figure:

IWR mode:

AT8.png

ITR mode:

AT9.png


After zooming in, the timing details at the trigger level ST are as follows:

AT10.png

The overall timing requirements are as follows:

Name

High level width

Initial level

Rising edge time

CLK

0.5 CLK cycle

Low

0.5 CLK cycle

RESET

Adjust   according to the integration time

High


SH1


Low

6μs

SH2

4μs

Low

5μs before RESET   falling edge

SH3

4μs

Low

1μs

ST

1   CLK cycle

Low

15μs

1) The CLK cycle and RESET high level width can be set according to the needs. The recommended CLK frequency range is 1~10MHz, and the RESET low level width cannot be less than 2μs;

2) In IWR mode, the order of SH1, SH2, and SH3 cannot be changed. The specific integration time of the detector is the time from the falling edge of SH1 to the falling edge of SH2 in the same RESET cycle;

3) The ST high level needs to cover a complete CLK high level, and the ST rising edge needs to be within the low level of CLK. It is recommended to set the rising edge at 1/2 of the CLK low level;

4) The actual signal is read from the first CLK rising edge after the ST rising edge. The reference signal R and the output signal S are read out in sequence until the last CLK cycle before the falling edge of SH2 is reached;

5) If the width of RESET high level is not enough to read out all 516 pixels, when the next RESET high level comes, it will still start reading from the first pixel, not from the pixel that has not been read; if the width of RESET high level is too large, it will continue to be empty after reading all 516 pixels of the channel, until the RESET low level comes to reset;

 6) It is recommended to use digital input voltage for SC1, SC2, and SC3, that is, always maintain 3.3V high level/0V low level;


Detector peripheral recommended circuit diagram

AT11.png


Thermal parameters

Thermoelectric Cooler Characteristics

The detector integrates a secondary thermoelectric cooler (TEC). The center of the heat dissipation surface is the center of the lower surface of the detector. The heat dissipation area should be ≥ 20mm×20mm. Its performance parameters are shown in the following table:

Performance Indicators

Value

Maximum temperature difference between hot and cold surfaces (△Tmax/℃)*

45

Maximum allowable load current (ITEC-max/A)

2.72

Maximum allowable load voltage (VTEC-max/V)

13.5

* This performance index refers specifically to the temperature difference between the focal plane and the heat dissipation surface of the package structure


Temperature Sensor Characteristics

This detector uses a thermistor as a temperature sensor. The relationship between the resistance value and temperature within the working temperature is shown in the figure below.

AT12.png




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